Four steps associative full adder
US10534836B2 · kind B2 · utility
7Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Dec 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/506
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes initiating the sum bit to the value of the second one bit variable, initiating the carry-out bit to a value of the carry-in bit and modifying the sum bit and the carry-out bit if a comparison of a sequence of the first one bit variable, the second one bit variable and an inverse value of the carry-in bit matches one of a predefined set of a change trigger sequences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.