LeeLean Shu
7Patents
6h-index
4Co-inventors
48Inventor score
Filing activity: Dec 9, 2011 → Jan 13, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8693236B2 | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features | Physics | 28 | Active |
| US9159391B1 | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features | Physics | 27 | Active |
| US8593860B2 | Systems and methods of sectioned bit line memory arrays | Physics | 26 | Active |
| US9431079B1 | Systems and methods of memory and memory operation involving input latching, self-timing and/or other features | Physics | 25 | Active |
| US9484076B1 | Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features | Physics | 24 | Active |
| US10534836B2 | Four steps associative full adder | Physics | 7 | Active |
| US11604850B2 | In-memory full adder | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.