Level shifter with bypass
US10535386B2 · kind B2 · utility
0Cited by
18References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.