DQS gating in a parallelizer of a memory device
US10535387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Apr 29, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.