Liang Chen
17Patents
5h-index
7Co-inventors
55Inventor score
Filing activity: Feb 18, 2009 → Oct 20, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8984214B2 | Memory cell operation | Physics | 19 | Active |
| US8195899B2 | Memory cell operation | Physics | 8 | Active |
| US9341596B1 | Annular gas ionization delta E-E detector | Physics | 8 | Active |
| US10679683B1 | Timing circuit for command path in a memory device | Emerging Cross-Sectional Technologies | 7 | Active |
| US10452319B1 | Write leveling a memory device | Physics | 7 | Active |
| US10373654B1 | Memory device with a signaling mechanism | Electricity | 4 | Active |
| US8402207B2 | Memory cell operation | Physics | 2 | Active |
| US10664173B2 | Write level initialization synchronization | Physics | 2 | Active |
| US10490241B2 | DFE conditioning for write operations of a memory device | Emerging Cross-Sectional Technologies | 2 | Active |
| US10672441B2 | Gap detection for consecutive write operations of a memory device | Emerging Cross-Sectional Technologies | 1 | Active |
| US10607671B2 | Timing circuit for command path in a memory device | Emerging Cross-Sectional Technologies | 1 | Active |
| US10825494B2 | DFE conditioning for write operations of a memory device | Emerging Cross-Sectional Technologies | 1 | Active |
| US11144241B2 | Write leveling a memory device | Physics | 0 | Active |
| US10535387B2 | DQS gating in a parallelizer of a memory device | Emerging Cross-Sectional Technologies | 0 | Active |
| US11456031B2 | Write leveling a memory device using write DLL circuitry | Physics | 0 | Active |
| US11675541B2 | Systems and methods for centralized address capture circuitry | Physics | 0 | Active |
| US11823729B2 | Command clock gate implementation with chip select signal training indication | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.