Device arrangement structure assembly and test method
US10535572B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.