High voltage CMOS with co-planar upper gate surfaces for embedded non-volatile memory

US10535675B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Wei-Cheng Wu · Hengshan, TW
• Ya-Chen Kao · Taoyuan, TW
• Yi Hsien Lu · Yuanchang, TW

Key dates

• Filing date: Apr 29, 2019
• Grant date: Jan 14, 2020
• Expiry date: Apr 29, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.