Semiconductor memory device and manufacturing method thereof
US10535677B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2018 |
| Grant date | Jan 14, 2020 |
| Priority date | — |
| Expiry date | Aug 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a conductive layer group including at least two conductive layers; a stacked body provided on the conductive layer group and including a plurality of films stacked; a memory film provided in a hole, the hole penetrating the stacked body and a part of the conductive layer group; and a slit splitting the stacked body and terminating at a position deeper than a contact portion between the conductive layer group and the memory film. The conductive layer group has a band-shaped part projecting to the stacked body side at a portion of the hole, and a groove part recessed to the semiconductor substrate side at a portion under the slit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.