Providing data of a memory system based on an adjustable error rate
US10540228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | May 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.