Inventor · Longmont, CO, US

Michael Sheperek

104Patents
7h-index
23Co-inventors
74Inventor score

Filing activity: Nov 17, 2003 → Jun 10, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7023647B2 Fly height control for a read/write head in a hard disk drive Physics 38 Expired
US7097110B2 Temperature compensation systems and methods for use with read/write heads in magnetic storage devices Physics 28 Expired
US9257145B1 Disk drive measuring down-track spacing of read sensors Physics 16 Active
US10566063B2 Memory system with dynamic calibration using a trim management mechanism Physics 13 Active
US11263134B1 Block family combination and voltage bin selection Emerging Cross-Sectional Technologies 8 Active
US11217320B1 Bin placement according to program-erase cycles Physics 8 Active
US10748625B1 Dynamic programing of valley margins of a memory cell Physics 7 Active
US10664194B2 Memory system with dynamic calibration using a variable adjustment mechanism Physics 6 Active
US11340813B1 Reliability scan assisted voltage bin selection Physics 6 Active
US11177006B2 Memory system with dynamic calibration using a trim management mechanism Physics 5 Active
US10540228B2 Providing data of a memory system based on an adjustable error rate Physics 5 Active
US10629278B2 First-pass dynamic program targeting (DPT) Physics 5 Active
US11416173B2 Memory system with dynamic calibration using a variable adjustment mechanism Physics 4 Active
US11211128B1 Performing threshold voltage offset bin selection by package for memory devices Physics 4 Active
US10936246B2 Dynamic background scan optimization in a memory sub-system Physics 3 Active
US11404139B2 Smart sampling for block family scan Physics 3 Active
US11270772B1 Voltage offset bin selection by die group for memory devices Physics 3 Active
US11301382B2 Write data for bin resynchronization after power loss Physics 2 Active
US11573720B2 Open block family duration limited by time and temperature Emerging Cross-Sectional Technologies 2 Active
US11443830B1 Error avoidance based on voltage distribution parameters of block families Physics 2 Active
US11003383B2 Estimation of read level thresholds using a data structure Physics 2 Active
US10885975B2 Dragging first pass read level thresholds based on changes in second pass read level thresholds Physics 1 Active
US11361825B2 Dynamic program erase targeting with bit error rate Physics 1 Active
US11404124B2 Voltage bin boundary calibration at memory device power up Physics 1 Active
US11886726B2 Block family-based error avoidance for memory devices Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.