Multi integrated circuit chip carrier package
US10541156B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned within a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment receptacles within the lid with one or more respective alignment protrusions of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, respective lid pedestals may be loaded toward respective IC chips, and an integral lid foot may be loaded toward the carrier. While under compression, thermal interface material between respective lid pedestals and respective IC chips and seal band material between the integral foot and the carrier may be cured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.