Patent · US Active

Method for fabricating stack die package

US10546840B2 · kind B2 · utility

3Cited by

56References

20Claims

0Family size

Assignee

Vishay-Siliconix, LLC · US

Inventors

Kyle Terrill · Santa Clara, US
Frank Kuo · Taipei, TW
Sen Mao

Key dates

Filing date	Feb 22, 2017
Grant date	Jan 28, 2020
Priority date	—
Expiry date	Feb 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.