Integrated assemblies having spacers of low permittivity along digit-lines, and methods of forming integrated assemblies
US10546862B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2019 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jan 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated assembly having active-region-pillars extending upwardly from a base. Each of the active-region-pillars has a pair of storage-element-contact-regions, and a digit-line-contact-region between the storage-element-contact-regions. The integrated assembly includes, along a cross-section, a first digit-line-contact-region adjacent a first storage-element-contact-region. The first digit-line-contact-region is recessed relative to the first storage-element-contact-region. A first digit-line is coupled with the first digit-line-contact-region. A second digit-line is laterally offset from the first digit-line. An insulative material is between the first digit-line and the first storage-element-contact-region. A cup-shaped indentation extends into the insulative material and the first storage-element-contact-region. Insulative spacers are along sidewalls of the first and second digit-lines, and include first material. First and second insulative pillars are over the first and second digit-lines, and include second material. Some embodiments include methods of forming integrated assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.