Three-dimensional memory device containing offset column stairs and method of making the same
US10546870B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional NAND memory string includes an alternating stack of insulating layers and word line layers extending in a word line direction, a memory array region in the alternating stack containing memory stack structures, a group of more than two column stairs located in the alternating stack and extending in the word line direction from one side of the memory array region, and bit lines electrically contacting the vertical semiconductor channels and extending in a bit line direction which is perpendicular to the word line direction. Each column stair of the group of N column stairs has a respective step in a first vertical plane which extends in the bit line direction, and the respective steps in the first vertical plane decrease and then increase from one end column stair to another end column stair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.