Semiconductor memory device including a capacitor
US10546875B2 · kind B2 · utility
2Cited by
12References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jun 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.