Optimized double-gate transistors and fabricating process
US10546929B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 19, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Jul 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a substrate; a buried insulating layer; at least one nMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one pMOS transistor comprising a semiconductor layer placed above the buried insulating layer; at least one semiconductor groundplane that may be doped or a metal, placed above the substrate and below the buried insulating layer, said buried plane being common to the nMOS transistor and to the pMOS transistor; at least one gate insulator and a gate that is common to the nMOS transistor and to the pMOS transistor and that is located above the channel of these transistors and facing the groundplane, the area of the groundplane at least covering the area of the gate in vertical projection; the nMOS transistor being separated from the pMOS transistor by an isolation defined between the semiconductor layer of the nMOS transistor and the semiconductor layer of the pMOS transistor, the isolation being located in the buried insulating layer and making contact with the groundplane; at least one shared contact making electrical contact with the common gate and with the common groundplane, the shared contact pas…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.