Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same
US10552087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.