Patent · US Active

Clock-gating for multicycle instructions

US10552167B2 · kind B2 · utility

0Cited by

11References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Juergen Haess · Schenefeld, DE
Cedric Lichtenau · Stuttgart, DE
Stefan Payer · Stuttgart, DE
Kerstin Claudia Schelm · Stuttgart, DE

Key dates

Filing date	Nov 27, 2017
Grant date	Feb 4, 2020
Priority date	—
Expiry date	Feb 22, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system and a method of clock-gating for multicycle instructions are provided. For example, the method includes enabling a plurality of logic blocks that include a subset of multicycle (MC) logic blocks and a subset of pipeline logic blocks. The method also includes computing a precise enable computation value after a plurality of cycles of executing an instruction, and disabling one or more of the subset of multicycle (MC) logic blocks based on the precise enable computation value. Also, at least the subset of pipeline logic blocks needed to compute the instruction remains on.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.