Systems and methods for semiconductor packages using photoimageable layers

US10553453B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Sri Chaitra Jyotsna Chavali · Chandler, US
• Siddharth K. Alur · Chandler, US
• Amanda E. Schuckman · Scottsdale, US
• Amruthavalli P. Alur · Chandler, US
• Islam A. Salama · Scottsdale, US
• Yikang Deng · New York, US
• Kristof Darmawikarta · Chandler, US

Key dates

• Filing date: Jul 14, 2016
• Grant date: Feb 4, 2020
• Expiry date: Jul 14, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15153
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimagable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.