Semiconductor memory device
US10553591B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 7, 2019 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Mar 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
Abstract
A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.