Three-dimensional memory device containing drain select isolation structures and on-pitch channels and methods of making the same without an etch stop layer
US10553599B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings and including a respective memory-level semiconductor channel and a respective memory film. Drain-select-level gate electrodes overlie the alternating stack. Drain-select-level pillar structures extend through a respective one of the drain-select-level gate electrodes. Each drain-select-level semiconductor channel is electrically connected to an underlying one of the memory-level semiconductor channels. A planar insulating spacer layer having a homogeneous composition throughout directly contacts top surfaces of the memory films and bottom surfaces of the drain-select-level gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.