Methods and apparatus for three-dimensional non-volatile memory
US10553647B2 · kind B2 · utility
3Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jul 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.