Forming a superjunction transistor device

US10553681B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Hans Weber · Villach, AT
• Franz Hirler · Isen, DE
• Maximilian Treiber · Munich, DE
• Daniel Tutuc · Finkenstein, AT
• Andreas Voerckel · Finkenstein, AT

Key dates

• Filing date: Aug 17, 2018
• Grant date: Feb 4, 2020
• Expiry date: Aug 17, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method includes forming first regions of a first doping type and second regions of a second doping type in first and second semiconductor layers such that the first and second regions are arranged alternately in at least one horizontal direction of the first and second semiconductor layers, and forming a control structure with transistor cells each including at least one body region, at least one source region and at least one gate electrode in the second semiconductor layer. Forming the first and second regions includes: forming trenches in the first semiconductor layer and implanting at least one of first and second type dopant atoms into sidewalls of the trenches; forming the second semiconductor layer on the first semiconductor layer such that the second layer fills the trenches; implanting at least one of first and second type dopant atoms into the second semiconductor layer; and at least one temperature process.