Transistor with controlled overlap of access regions
US10553702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.