FinFETs having gates parallel to fins

US10553707B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Yanping Shen · Saratoga Springs, US
• Hui Zang · Guilderland, US
• Bingwu Liu · Ballston Spa, US
• Manoj Joshi · Clifton Park, US
• Jae Gon Lee · Singapore, SG
• Hsien-Ching Lo · Clifton Park, US
• Zhaoying Hu · Clifton Park, US

Key dates

• Filing date: Aug 22, 2018
• Grant date: Feb 4, 2020
• Expiry date: Aug 22, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.