Memory element graph-based placement in integrated circuit design
US10558775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Mar 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to perform physical synthesis to transition a logic design to a physical layout of an integrated circuit include obtaining an initial netlist that indicates all components of the integrated circuit including memory elements and edges that interconnect the components. The method also includes generating a graph with at least one of the memory elements and the edges carrying one or more signals to the at least one of the memory elements or from the at least one of the memory elements. The components other than memory elements are not indicated individually on the graph. The netlist is updated based on the graph.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.