Peak current suppression
US10559365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Jun 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.