Non-volatile memory with countermeasures for select gate disturb during program pre-charge
US10559368B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 7, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Program disturb is a condition that includes the unintended programming while performing a programming process for memory cells, where the program disturb can affect both memory cells and select gates in a NAND structure. During a pre-charge phase of a programming operation, a drain side select gate may be biased to a higher voltage than an adjacent word line, resulting in a disturb of the select gate due to hot-electron injection. This can raise the threshold voltage of the select gate, causing error in reading the NAND string or even making it inaccessible. To help avoid this problem, during a program pre-charge, the voltage applied to the select gate is raised in a sequence of steps, rather than driving the select gate directly to its final pre-charge voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.