Methods of forming a channel region of a transistor and methods used in forming a memory array
US10559466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.