Two-level tape frame rinse assembly
US10559488B2 · kind B2 · utility
2Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68742
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A two-level tape frame rinse assembly is configured for grasping the substrate so as to create a gap between the substrate and a backside support plate that allows the backside of the wafer to be rinsed and spun dry after rinsing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.