Molded wafer level packaging

US10559510B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Soon Wei WANG · Seremban, MY
• Jin Yoong LIONG · Seremban, MY
• Chee Hiong CHEW · Seremban, MY
• Francis J. Carney · Mesa, US

Key dates

• Filing date: Nov 14, 2017
• Grant date: Feb 11, 2020
• Expiry date: Nov 14, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1816
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.