Soon Wei WANG
35Patents
3h-index
16Co-inventors
56Inventor score
Filing activity: Mar 17, 2008 → Jun 13, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10199311B2 | Leadless semiconductor packages, leadframes therefor, and methods of making | Electricity | 5 | Active |
| US9281258B1 | Chip scale packages and related methods | Electricity | 4 | Active |
| US8451621B2 | Semiconductor component and method of manufacture | Emerging Cross-Sectional Technologies | 3 | Active |
| US7939380B2 | Method of manufacturing a semiconductor component with a low cost leadframe using a non-metallic base structure | Electricity | 3 | Active |
| US8449339B2 | Connector assembly and method of manufacture | Emerging Cross-Sectional Technologies | 3 | Active |
| US10756006B2 | Leadless semiconductor packages, leadframes therefor, and methods of making | Electricity | 1 | Active |
| US10825754B2 | Quad flat no leads package with locking feature | Electricity | 1 | Active |
| US11532539B2 | Semiconductor package with wettable flank | Electricity | 1 | Active |
| US10930604B2 | Ultra-thin multichip power devices | Electricity | 1 | Active |
| US9748163B1 | Die support for enlarging die size | Electricity | 1 | Active |
| US11721654B2 | Ultra-thin multichip power devices | Electricity | 1 | Active |
| US11404276B2 | Semiconductor packages with thin die and related methods | Electricity | 0 | Active |
| US10559510B2 | Molded wafer level packaging | Electricity | 0 | Active |
| US10971429B2 | Method for forming a semiconductor package | Electricity | 0 | Active |
| US12374554B2 | Semiconductor packages with die including cavities and related methods | Electricity | 0 | Active |
| US10438877B1 | Multi-chip packages with stabilized die pads | Electricity | 0 | Active |
| US11361970B2 | Silicon-on-insulator die support structures and related methods | Electricity | 0 | Active |
| US11901184B2 | Backmetal removal methods | Emerging Cross-Sectional Technologies | 0 | Active |
| US12040192B2 | Die sidewall coatings and related methods | Electricity | 0 | Active |
| US11348796B2 | Backmetal removal methods | Emerging Cross-Sectional Technologies | 0 | Active |
| US10283466B2 | Polymer resin and compression mold chip scale package | Electricity | 0 | Active |
| US10607920B2 | Semiconductor package | Electricity | 0 | Active |
| US11404277B2 | Die sidewall coatings and related methods | Electricity | 0 | Active |
| US12176272B2 | Semiconductor package with wettable flank | Electricity | 0 | Active |
| US11508679B2 | Polymer resin and compression mold chip scale package | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.