Vertical transport field-effect transistor including air-gap top spacer

US10559671B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Hemanth Jagannathan · Niskayuna, US
• Choonghyun Lee · Rensselaer, US
• Alexander Reznicek · Troy, US
• Christopher J. Waskiewicz · Rexford, US

Key dates

• Filing date: May 6, 2019
• Grant date: Feb 11, 2020
• Expiry date: May 6, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/679

Abstract

A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.