Texture breaking layer to decouple bottom electrode from PMTJ device

US10559744B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Brian Maertz · Lompoc, US
• Christopher J. Wiegand · Portland, US
• Daniel G. Oeullette · Portland, US
• MD Tofizur Rahman · Portland, US
• Oleg Golonzka · Beaverton, US
• Justin S. Brockman · Portland, US
• Tahir Ghani · Portland, US
• Brian S. Doyle · Portland, US
• Kevin P. O'Brien · Cincinnati, US
• Mark L. Doczy · Beaverton, US
• Kaan Oguz · Beaverton, US

Key dates

• Filing date: Apr 1, 2016
• Grant date: Feb 11, 2020
• Expiry date: Apr 1, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85

Abstract

An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.