Selectively disconnecting a memory cell from a power supply
US10566050B1 · kind B1 · utility
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15References
20Claims
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Key dates
| Filing date | Mar 21, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Mar 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.