Memory device and program/erase method therefor
US10566060B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 24, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Dec 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided and includes a status register, a memory array, a memory controller, an interface control circuit, and a write control logic circuit. The status register stores a plurality of status bits and a first threshold. The interface control circuit is controlled by the memory controller to perform a data program/erase operation on the memory array and re-program/re-erase the memory array in a retry mode when the data program/erase operation is not complete. The write control logic circuit counts the number of times the memory array is re-programmed/re-erased in the retry mode to generate a retry counting value, compares the retry counting value with the first threshold to generate a result signal. The status register updates a result bit included in the status bits according to the result signal. The memory controller determines whether the data program/erase operation is successful according to the result bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.