Microelectronic packages having stacked die and wire bond interconnects
US10566310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.