Kyong-Mo Bang
27Patents
6h-index
22Co-inventors
69Inventor score
Filing activity: Aug 13, 2003 → Jul 25, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7294928B2 | Components, methods and assemblies for stacked packages | Electricity | 140 | Expired |
| US8680684B2 | Stackable microelectronic package structures | Electricity | 87 | Active |
| US7246431B2 | Methods of making microelectronic packages including folded substrates | Emerging Cross-Sectional Technologies | 86 | Expired |
| US7053485B2 | Microelectronic packages with self-aligning features | Electricity | 76 | Expired |
| US9349707B1 | Contact arrangements for stackable microelectronic package structures with multiple ranks | Electricity | 23 | Active |
| US9484080B1 | High-bandwidth memory application with controlled impedance loading | Electricity | 8 | Active |
| US8980693B2 | Stackable microelectronic package structures | Electricity | 4 | Active |
| US7935569B2 | Components, methods and assemblies for stacked packages | Electricity | 3 | Active |
| US9425167B2 | Stackable microelectronic package structures | Electricity | 3 | Active |
| US9337170B1 | Contact arrangements for stackable microelectronic package structures | Electricity | 3 | Active |
| US9543277B1 | Wafer level packages with mechanically decoupled fan-in and fan-out areas | Electricity | 2 | Active |
| US9847238B2 | Fan-out wafer-level packaging using metal foil lamination | Electricity | 2 | Active |
| US10566310B2 | Microelectronic packages having stacked die and wire bond interconnects | Electricity | 1 | Active |
| US9281296B2 | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design | Electricity | 1 | Active |
| US9646946B2 | Fan-out wafer-level packaging using metal foil lamination | Electricity | 1 | Active |
| US9679613B1 | TFD I/O partition for high-speed, high-density applications | Electricity | 1 | Active |
| US10008469B2 | Wafer-level packaging using wire bond wires in place of a redistribution layer | Electricity | 1 | Active |
| US12322677B1 | Fluid channel geometry optimizations to improve cooling efficiency | Electricity | 0 | Active |
| US10468380B2 | Stackable microelectronic package structures | Electricity | 0 | Active |
| US9928883B2 | TFD I/O partition for high-speed, high-density applications | Electricity | 0 | Active |
| US9343398B2 | BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail | Electricity | 0 | Active |
| US12341083B2 | Electronic device cooling structures bonded to semiconductor elements | Electricity | 0 | Active |
| US12191234B2 | Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same | Electricity | 0 | Active |
| US9911717B2 | Stackable microelectronic package structures | Electricity | 0 | Active |
| US10026467B2 | High-bandwidth memory application with controlled impedance loading | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.