Three-dimensional memory devices having through array contacts and methods for forming the same
US10566336B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Oct 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed on a sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed after forming the TAC. A memory stack including a plurality of conductor/dielectric layer pairs is formed on the substrate by replacing, through the slit, the sacrificial layers in the dielectric/sacrificial layer pairs with a plurality of conductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.