Mitigation of hot carrier damage in field-effect transistors
US10566446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.