Circuit arrangements and methods for performing multiply-and-accumulate operations
US10572225B1 · kind B1 · utility
11Cited by
2References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/20084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A and a request generator circuit is configured to read data elements of a three-dimensional (3-D) input feature map (IFM) from a memory and store a subset of the data elements in one of a plurality of N line buffers. Each line buffer is configured for storage of M data elements. A pixel iterator circuit is coupled to the line buffers and is configured to generate a sequence of addresses for reading the stored data elements from the line buffers based on a sequence of IFM height values and a sequence of IFM width values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.