System and method for aligning semiconductor device reference images and test images
US10572991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Feb 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V2201/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method may include, but is not limited to, receiving a plurality of reference images of a wafer. The method may include, but is not limited to, receiving the plurality of test images of the wafer. The method may include, but is not limited to, aligning the plurality of reference images and the plurality of test images via a coarse alignment process. The method may include, but is not limited to, aligning the plurality of reference images and the plurality of test images via a fine alignment process after alignment via the coarse alignment process. The fine alignment process may include measuring individual offsets and correcting individual offset data between at least one of the plurality of reference images and the plurality of test images.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.