Method of charge controlled patterning during reactive ion etching
US10573526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Nov 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma processing apparatus for reactive ion etching a wafer includes a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges. Also provided is an anode comprising the plasma, a cathode comprising the wafer chuck, and a gate comprising the peripheral edge of the n+ layer. A coating layer is formed on a portion of the peripheral edge of the n+ layer. The coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.