Clock circuit and method of operating the same
US10574213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.