System and method for providing a configurable timing control for a memory system
US10580465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Feb 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.