Michael L. Takefman
30Patents
8h-index
18Co-inventors
72Inventor score
Filing activity: Nov 29, 1990 → Dec 15, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8615599B1 | Method and apparatus for preventing loops in a network by controlling broadcasts | Electricity | 312 | Active |
| US8713379B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 79 | Active |
| US8738853B2 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Physics | 67 | Active |
| US8452917B2 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Physics | 63 | Active |
| US5285527A | Predictive historical cache memory | Physics | 50 | Expired |
| US5761197A | Communications in a distribution network | Electricity | 38 | Expired |
| US5835036A | Method of encoding data for transmission | Electricity | 24 | Expired |
| US9552175B2 | System and method for providing a command buffer in a memory system | Electricity | 11 | Active |
| US9015408B2 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Physics | 6 | Active |
| US10580465B2 | System and method for providing a configurable timing control for a memory system | Physics | 6 | Active |
| US7453873B1 | Methods and apparatus for filtering packets for preventing packet reorder and duplication in a network | Electricity | 4 | Expired |
| US9444495B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 4 | Active |
| US9449651B2 | System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset | Physics | 3 | Active |
| US8972805B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 1 | Active |
| US11061841B2 | System and method for implementing a multi-threaded device driver in a computer system | Physics | 1 | Active |
| US9575908B2 | System and method for unlocking additional functions of a module | Physics | 1 | Active |
| US10168954B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 1 | Active |
| US11789662B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 0 | Active |
| US9088484B1 | Method and apparatus for preventing loops in a network by controlling broadcasts | Electricity | 0 | Active |
| US7742410B1 | Methods and apparatus for using gap packets to create a bandwidth buffer over which packets can be sent to reduce or eliminate overflow conditions | Electricity | 0 | Active |
| US10942682B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 0 | Active |
| US11422749B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 0 | Active |
| US10725704B2 | System and method of interfacing co-processors and input/output devices via a main memory system | Physics | 0 | Active |
| US10719466B2 | System and method for implementing a multi-threaded device driver in a computer system | Physics | 0 | Active |
| US9465557B2 | Load reduction dual in-line memory module (LRDIMM) and method for programming the same | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.