Patent · US Active

Method of reducing trench depth variation from reactive ion etching process

US10580656B2 · kind B2 · utility

0Cited by

1References

28Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Marija Borna Tutuc · Villach, AT
Daniel Tutuc · Finkenstein, AT
Andrew Christopher Graeme Wood · St. Jakob im Rosental, AT

Key dates

Filing date	Jul 6, 2018
Grant date	Mar 3, 2020
Priority date	—
Expiry date	Jul 6, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/117
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor wafer having a main surface is provided. A first etch resistant mask is provided on the main surface. A first reactive ion etching step that forms a first group of trenches using the first etch resistant mask is performed. Each of the trenches in the first group is covered with a second etch resistant mask after performing the first reactive ion etching step. A second reactive ion etching step that forms a second group of trenches using one or both of the first etch resistant mask and the second etch resistant mask is performed. The trenches in the second group are laterally offset from the trenches in the first group. The first and second reactive ion etching processes are performed such that a depth of the trenches of the first group is substantially equal to a depth of the trenches in the second group.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.