Semiconductor structure for electrostatic discharge protection
US10580765B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Dec 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A semiconductor structure includes a silicon control rectifier (SCR) region and a NPN region adjacent to the SCR region. The silicon control rectifier (SCR) region includes a first p-well region, a first n-well region surrounded by the first p-well region and a first P+ region in the first p-well region and spaced apart from the first n-well region. The NPN region includes a second p-well region, a first N+ region, a second N+ region and a second P+ region. The first N+ region is coupled to the second p-well region and an electrostatic discharge source. The second N+ region is coupled to the second p-well region and spaced apart from the first N+ region. The second P+ region is disposed in the second p-well region and equipotentially connected to the first P+ region in the first p-well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.