Trench semiconductor device layout configurations
US10580861B2 · kind B2 · utility
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51References
9Claims
0Family size
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Key dates
| Filing date | Feb 20, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Feb 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.