Integrated circuit with memory cells having reliable interconnection
US10580968B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Oct 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region and a second region. The first region includes a memory region having at least one magnetic tunnel junction (MTJ) stack, and the second region includes a logic region. An encapsulation stack is formed in the first and second regions and over the MTJ stack(s). The encapsulation stack includes a first layer, a second layer, and a third layer. A single etch may remove at least a portion of the third layer, the second layer, and the first layer of the encapsulation stack to form a self-aligned MTJ via opening over the at least one MTJ stack to form one or more peaks from the encapsulation stack above or around the MTJ stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.